The present invention relates to a technology effectively applicable to a rewiring peripheral structure of a semiconductor integrated circuit device, and a rewiring peripheral processing technology in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).
In Japanese Unexamined Patent Publication No. 2004-200195 (Patent Document 1), there is disclosed a technology of performing a coating processing with a polyimide resin or the like, and a dicing processing after formation of bump electrodes in the wafer level package process.
In a published Japanese translation of a PCT patent application No. 2005-538572 (Patent Document 2) or U.S. Pat. No. 6,649,445 (Patent Document 3), there is disclosed a technology in which after the formation of bump electrodes, the wafer is subjected to half dicing, and is coated with an underfill such as polyimide, and finally, is separated into chips in the wafer level package process.
[Patent Document 1]    Japanese Unexamined Patent Publication No. 2004-200195
[Patent Document 2]    Published Japanese translation of a PCT patent application No. 2005-538572
[Patent Document 3]    U.S. Pat. No. 6,649,445